1. Field of the Invention
This invention generally relates to a signal sample and hold circuit, and especially to a sample and hold circuit, which prevents sample distortion caused by charge distribution effect.
2. Description of Related Art
A conventional circuit structure of sampling and holding information is shown in FIG. 1, wherein an operational amplifier 103 for example includes an input stage 104 and an output stage 105. In a sample period, a switch 101 is conducted and a switch 102 is un-conducted, meanwhile an input signal Vin is stored in a capacitor 106. Therefore the voltage at node N1 is Vin, and the capacitor 106 stores a charge amount of C1. In a hold period, the switch 101 is un-conducted and the switch 102 is conducted, therefore, owing to the charge distribution effect, a portion of charges stored in the capacitor 106 flowing to a parasitic capacitor, represented by Cp1, between a gate electrode of a positive input terminal of the input stage 104 and ground. It means that a voltage at node N2 equals to C1Vin/(C1+Cp1). Therefore, the voltage level of the output signal Vout of the operational amplifier 103 will become C1Vin/(C1+Cp1) rather than the voltage level Vin of the previous sample due to the charge distribution effect.
Another conventional sample and hold circuit is shown as FIG. 2, including a plurality of switches 201 to 204, a plurality of sample capacitors 205 and 206, and an operational amplifier 207. The operational amplifier 207 for example includes an input stage 208 and an output stage 209. The non-overlapping clocks are utilized to turn on and turn off the switches 201 to 204. In the first period, the switches 201 and 204 are conducted and the switches 202 and 203 are un-conducted, meanwhile an input information is stored in the capacitor 205, and the output voltage Vout is obtained from the information stored in the capacitor 206. Further in the second period, the switches 202 and 203 are conducted and the switches 201 and 204 are un-conducted, meanwhile the output voltage Vout is obtained from the information stored in the capacitor 205, and next an input information will be stored in the capacitor 206. However, in the ample and hold circuit shown as FIG. 2, there existing a disadvantage of voltage level distortion of Vout due to the charge distribution effect.